Invention Grant
- Patent Title: Memory system capable of performing a data clock calibration operation
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Application No.: US16396215Application Date: 2019-04-26
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Publication No.: US10734045B2Publication Date: 2020-08-04
- Inventor: Young-Dong Roh
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@36dc901b
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C7/06 ; G11C8/06 ; G06F3/06 ; G11C8/18 ; G11C29/02 ; G11C29/36 ; G11C29/52 ; G11C7/10

Abstract:
A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.
Public/Granted literature
- US20190252012A1 MEMORY SYSTEM Public/Granted day:2019-08-15
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