A second-order ΔΣ modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.