Invention Grant
- Patent Title: Processing stacked substrates
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Application No.: US15846731Application Date: 2017-12-19
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Publication No.: US10707087B2Publication Date: 2020-07-07
- Inventor: Cyprian Emeka Uzoh , Guilian Gao
- Applicant: Invensas Bonding Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Invensas Bonding Technologies, Inc.
- Current Assignee: Invensas Bonding Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/683 ; H01L21/78 ; H01L21/02

Abstract:
Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.
Public/Granted literature
- US20180182639A1 Processing Stacked Substrates Public/Granted day:2018-06-28
Information query
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