A circuit for generating a sampling signal for a UART interface has an input terminal designed to receive a peripheral clock, an output terminal designed to output the sampling signal, a bit rate memory designed to store a value corresponding to a desired bit rate of the UART interface, a peripheral clock memory designed to store a value corresponding to a frequency of the peripheral clock, a sum memory designed to store a sum value, and a computing unit. The computing unit compares a comparison value, which is dependent on the sum value stored in the sum memory, with a threshold value, which is dependent on the value stored in the peripheral clock memory. The result of the comparison is taken as a basis for generating the sampling signal at a first level or a second level. In step with the peripheral clock and on the basis of the result of the comparing, the sum value stored in the sum memory is altered by the value stored in the bit rate memory or the sum value stored in the sum memory is altered by a value that is dependent on the value stored in the peripheral clock memory.