Invention Grant
- Patent Title: Memory system with LDPC decoder and method of operating such memory system and LDPC decoder
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Application No.: US16010026Application Date: 2018-06-15
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Publication No.: US10693496B2Publication Date: 2020-06-23
- Inventor: Naveen Kumar , Aman Bhatia , Chenrong Xiong , Yu Cai , Fan Zhang
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; G06F11/10 ; G06N3/04 ; G06N3/08 ; G11C29/52 ; G11C29/04

Abstract:
A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.
Public/Granted literature
- US20190068220A1 MEMORY SYSTEM WITH LDPC DECODER AND METHOD OF OPERATING SUCH MEMORY SYSTEM AND LDPC DECODER Public/Granted day:2019-02-28
Information query
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