Invention Grant
- Patent Title: Clock generation system and method having time and frequency division activation mechanism
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Application No.: US16526066Application Date: 2019-07-30
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Publication No.: US10693478B2Publication Date: 2020-06-23
- Inventor: Jui-Chang Tsao , Chen-Kuo Hwang , Po-Wei Liu
- Applicant: Realtek Semiconductor Corporation
- Applicant Address: TW Hsinchu
- Assignee: REALTEK SEMICONDUCTOR CORPORATION
- Current Assignee: REALTEK SEMICONDUCTOR CORPORATION
- Current Assignee Address: TW Hsinchu
- Agency: Locke Lord LLP
- Agent Tim Tingkang Xia, Esq.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@f4e1684
- Main IPC: H03L7/18
- IPC: H03L7/18 ; G06F1/04 ; H03L7/08

Abstract:
A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
Public/Granted literature
- US20200052707A1 CLOCK GENERATION SYSTEM AND METHOD HAVING TIME AND FREQUENCY DIVISION ACTIVATION MECHANISM Public/Granted day:2020-02-13
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