A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a lower electrode layer and a second dielectric layer; forming a piezoelectric film and an upper electrode layer in an opening in the second dielectric layer; forming a third dielectric layer; forming a first cavity in the third dielectric layer to expose at least part of the upper electrode layer; bonding a first assistant substrate to seal the first cavity; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer on a side of the isolation trench; and etching through the fourth dielectric layer, the isolation trench layer, the first dielectric layer to form a second cavity beneath the lower electrode layer, plan views of the first and second cavities providing an overlapped region having a polygon shape without parallel sides.