Invention Grant
- Patent Title: Semiconductor device and manufacturing method of the same
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Application No.: US15091009Application Date: 2016-04-05
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Publication No.: US10693013B2Publication Date: 2020-06-23
- Inventor: Satoshi Toriumi , Takashi Hamada , Tetsunori Maruyama , Yuki Imoto , Yuji Asano , Ryunosuke Honda , Shunpei Yamazaki
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@35da994a com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@11e39b6d
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/24 ; H01L29/51 ; H01L29/49 ; H01L29/417 ; H01L27/12 ; H01L27/146 ; H01L27/1156 ; H01L27/06 ; H01L29/423 ; H01L21/822

Abstract:
A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.
Public/Granted literature
- US20160300952A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME Public/Granted day:2016-10-13
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