Invention Grant
- Patent Title: Semiconductor device and method for manufacturing the same
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Application No.: US15081251Application Date: 2016-03-25
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Publication No.: US10693012B2Publication Date: 2020-06-23
- Inventor: Yoshinobu Asami
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@265ea499
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/423 ; H01L29/66 ; H01L21/02 ; H01L21/465 ; H01L21/3115 ; H01L21/469 ; H01L27/12

Abstract:
A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.
Public/Granted literature
- US20160284859A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2016-09-29
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