Invention Grant
- Patent Title: Method and structure for FinFET device
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Application No.: US16217113Application Date: 2018-12-12
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Publication No.: US10692867B2Publication Date: 2020-06-23
- Inventor: Kuo-Cheng Ching , Ka-Hing Fung , Chih-Sheng Chang , Zhiqiang Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/092 ; H01L29/16 ; H01L29/165 ; H01L29/161 ; H01L29/49 ; H01L29/51 ; H01L21/02 ; H01L21/8238 ; H01L29/66 ; H01L21/306 ; H01L21/311 ; H01L29/78 ; H01L29/167 ; H01L29/06

Abstract:
The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.
Public/Granted literature
- US20190123050A1 Method and Structure for FinFET Device Public/Granted day:2019-04-25
Information query
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