Invention Grant
- Patent Title: Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages
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Application No.: US16036067Application Date: 2018-07-16
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Publication No.: US10692866B2Publication Date: 2020-06-23
- Inventor: Takashi Ando , Jingyun Zhang , Choonghyun Lee , Pouya Hashemi , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/786 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L21/8238 ; H01L21/02 ; H01L21/28 ; H01L21/3215

Abstract:
Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method including performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate. The first fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first channel nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure. A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.
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