Invention Grant
- Patent Title: Method of manufacturing semiconductor device
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Application No.: US16366529Application Date: 2019-03-27
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Publication No.: US10692751B2Publication Date: 2020-06-23
- Inventor: Toshiaki Sakata , Takeyoshi Nishimura , Isamu Sugai , Kazuya Yamaguchi
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@1464ba80
- Main IPC: H01L21/761
- IPC: H01L21/761 ; H01L21/265 ; H01L21/266 ; H01L21/225 ; H01L29/06 ; H01L21/3065 ; H01L21/02 ; H01L21/324

Abstract:
In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.
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