A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.