Invention Grant
- Patent Title: Low power VTT generation mechanism for receiver termination
-
Application No.: US16140356Application Date: 2018-09-24
-
Publication No.: US10692545B2Publication Date: 2020-06-23
- Inventor: Milam Paraschou , Balwinder Singh , Gerald R. Talbot , Alushulla Jack Ambundo , Edoardo Prete , Thomas H. Likens, III , Michael A. Margules
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kowert Hood Munyon Rankin and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C5/14 ; G11C11/4074 ; H04L25/02 ; H03K17/687

Abstract:
Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
Public/Granted literature
- US20200098399A1 LOW POWER VTT GENERATION MECHANISM FOR RECEIVER TERMINATION Public/Granted day:2020-03-26
Information query