An image processing apparatus includes a memory and circuitry. The circuitry is configured to calculate a pixel scale factor for each of pixel positions in a main scanning direction of an input image for a line based on a magnification. The circuitry is configured to store, in the memory, the pixel scale factors calculated for the line in order of pixel position. The circuitry is configured to read, in parallel, N-number of pixel scale factors of the pixel scale factors for the line in order of pixel position from the memory, in synchronization with parallel reading of N-number of pixels in the main scanning direction from the input image, where N represents an integer not smaller than 2. The circuitry is configured to multiply, in parallel, the N-number of pixels read from the input image by the respective N-number of pixel scale factors read from the memory.