A superposition circuitry superposes a dither signal on a reference DC bias voltage and outputs a resultant voltage as a bias voltage to an MZ modulator, during control of a driving voltage amplitude. During the control of the driving voltage amplitude to the MZ modulator, an amplitude setter determines, by varying the amplitude of an output voltage from an amplifier, a plurality of amplitudes of output curves from a synchronous detector, each of which is obtained by varying the reference DC bias voltage output from a bias controller, and the amplitude setter sets the amplification factor of the amplifier, based on an amplitude of the output voltage from the amplifier that corresponds to an amplitude satisfying a predetermined condition, out of the plurality of the amplitudes of the output curves from the synchronous detector.