A device using parity for verification of data transmitted from a first device through a data line to a second device includes a processor and a memory. The data line includes first to fourth pins for transmitting data and fifth to eighth pins for transmitting parity information. The processor receives values of first to eighth pins, calculates sum of the values of combinations of the first to fourth pins for data and applies modular operations on results of the four combinations. Equality or non-equality with the parity values of the fifth to eighth pins is determined, and the second device is permitted to receive the data when the results correspond, the modular operation being a (mod 2) operation. A method applied to such device is also disclosed.