Different delay counts are supplied to a counter to perform multiple frequency captures on the output of a phase-locked loop (PLL) device. A PLL frequency set signal is supplied to the counter for each of the multiple captures performed on the PLL device. The set signal causes the PLL device to transition from a relatively lower frequency state to a relatively higher target (lock) frequency state. A different time delay count is begun each time the set signal is detected at an input of the counter, and a trigger signal is output from the counter each time each of the different delay counts is complete. A frequency detector captures the frequency being output by the PLL device each time the trigger signal is received. Such forms a record of the frequency being output by the PLL device for each different time delay count.