A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.