A storage device includes a first memory chip including a first input pad configured to receive a first input signal, a first initializing circuit configured to generate a first initializing signal, a first input delay circuit configured to delay the first input signal by a first time to generate a first output signal, a first output pad configured to receive the first output signal and output the first output signal, a first clock delay circuit configured to delay the first initializing signal by a second time to generate a first clock signal, a second clock delay circuit configured to delay the first clock signal by a third time to generate a second clock signal, a first latch configured to store the first input signal based on the first clock signal, and a second latch configured to store the first input signal based on the second clock signal.