Invention Grant
- Patent Title: System, method, and computer program product for displaying bump layout for manufacturing variations
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Application No.: US16147832Application Date: 2018-09-30
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Publication No.: US10685167B1Publication Date: 2020-06-16
- Inventor: Jean-François Alain Lepère , Arnold Ginetti
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger, Esq.
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F3/0484 ; G06F119/18 ; G06F111/04 ; G06F111/20

Abstract:
The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may further include allowing a user to insert, at the graphical user interface prior to signoff, a copper pillar bump or solder bump on at least a portion of the layout based upon, at least in part, the determined expected thermal or centrifuge force manufacturing variation. Embodiments may further include displaying the copper pillar bump or the solder bump on the layout at the graphical user interface.
Information query