Invention Grant
- Patent Title: Semiconductor arrangement and formation thereof
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Application No.: US16443174Application Date: 2019-06-17
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Publication No.: US10683204B2Publication Date: 2020-06-16
- Inventor: Chung-Yen Chou , Lee-Chuan Tseng , Chia-Shiung Tsai , Ru-Liang Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Applicant Address: TW Hsin-chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsin-chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; B81C1/00

Abstract:
A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
Public/Granted literature
- US20190367358A1 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF Public/Granted day:2019-12-05
Information query
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