Invention Grant
- Patent Title: Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
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Application No.: US16401511Application Date: 2019-05-02
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Publication No.: US10672735B2Publication Date: 2020-06-02
- Inventor: Basil Milton , Wei Qin
- Applicant: Kulicke and Soffa Industries, Inc.
- Applicant Address: US PA Fort Washington
- Assignee: Kulicke and Soffa Industries, Inc.
- Current Assignee: Kulicke and Soffa Industries, Inc.
- Current Assignee Address: US PA Fort Washington
- Agent Christopher M. Spletzer, Sr.
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/00 ; H01L23/528
Abstract:
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Public/Granted literature
Information query
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