- Patent Title: Segmentation superposition technique for binary error compensation
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Application No.: US15940300Application Date: 2018-03-29
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Publication No.: US10666267B2Publication Date: 2020-05-26
- Inventor: Chao Chieh Li , Chia-Chun Liao , Min-Shueh Yuan , Robert Bogdan Staszewski
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: Jones Day
- Main IPC: H03L1/02
- IPC: H03L1/02 ; H03B5/08 ; H03L7/099 ; H03L1/00

Abstract:
Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.
Public/Granted literature
- US20190068199A1 Segmentation Superposition Technique for Binary Error Compensation Public/Granted day:2019-02-28
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