Elimination of secondary fuses in high power solid state power controllers
Abstract:
Embodiments include a technique for eliminating secondary fuses in high power solid state power controllers, the technique includes controlling gate power provided to a field effect transistor array, and detecting a failure mode. The technique also includes disabling the gate power based at least in part on detecting the failure mode, and restoring the gate power responsive to resolving the failure mode.
Information query
Patent Agency Ranking
0/0