Vertical transistors having improved gate length control
Abstract:
Embodiments of the invention form a channel fin across from a major surface of a substrate, wherein a top surface of the channel fin extends substantially horizontally with respect to the major surface. A gate is formed across from the major surface and along a sidewall surface of the channel fin, wherein a first top surface of the gate is above the top surface of the channel fin and extends substantially horizontally with respect to the major surface. A second top surface of the gate is defined by a trench formed through an exposed sidewall portion of the gate in a direction that is substantially horizontal with respect to the major surface, wherein a gate length dimension of the initial gate is defined by a distance from a bottom surface of the gate to the second top surface of the gate.
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