Invention Grant
- Patent Title: Semiconductor memory device and method for manufacturing same
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Application No.: US16128655Application Date: 2018-09-12
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Publication No.: US10665598B2Publication Date: 2020-05-26
- Inventor: Satoshi Nagashima , Shinya Arai
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@1dbbc827
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L27/11519 ; H01L27/11529 ; H01L27/11548 ; H01L27/11565 ; H01L27/11575 ; H01L27/11582 ; H01L21/768 ; H01L27/11573 ; H01L21/3213

Abstract:
A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.
Public/Granted literature
- US20190326309A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME Public/Granted day:2019-10-24
Information query
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