Provided are a drive circuit and a display apparatus capable of suppressing the delay of a drive signal. Each of multiple shift registers comprises: an output switching element to which a predetermined clock signal to be input, the output switching element comprising a second controlled terminal is connected to an output node from which a drive signal is output; a first input switching element comprising a first controlled terminal to which a set signal to be input and a second controlled terminal connected to the output switching element; and a control unit for applying a predetermined electric potential to the second controlled terminal of the output switching element, wherein a low-level electric potential of the predetermined clock signal is lower than a low-level electric potential of the drive signal, and the predetermined electric potential is applied to the output switching element when the predetermined clock signal falls.