Invention Grant
- Patent Title: Multi-core lock-free rate limiting apparatus and method
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Application No.: US15415329Application Date: 2017-01-25
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Publication No.: US10659372B2Publication Date: 2020-05-19
- Inventor: Wei Xu , Xiaofeng Yang , Yan Sun , Yizhen Liu , Zhe Fu , Zhi Liu , Jun Li
- Applicant: Futurewei Technologies, Inc.
- Applicant Address: US TX Plano
- Assignee: Futurewei Technologies, Inc.
- Current Assignee: Futurewei Technologies, Inc.
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: H04L12/851
- IPC: H04L12/851 ; H04L12/935 ; H04L12/863 ; H04L12/819

Abstract:
An apparatus, such as a network element, comprises a receiver to receive a plurality of packets. A memory stores instructions and forms a first and second set of virtual queues to store the plurality of packets. A processor having one or more cores with one or more packet classifiers provides a classification of a packet in the plurality of packets. The processor in communication with the memory executes instructions to transfer the packet from the receiver to a virtual queue in the first set of virtual queues based on the classification. The processor also transfers the packet from the virtual queue to a transmitter based on a demand rate value and supply rate value associated with the virtual queue.
Public/Granted literature
- US20180212889A1 MULTI-CORE LOCK-FREE RATE LIMITING APPARATUS AND METHOD Public/Granted day:2018-07-26
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