A 3D semiconductor wafer, the wafer including: a first device, where the first device includes a first level, the first level including first transistors, and where the first device includes a second level, the second level including first interconnections; a second device overlaying the first device, where the second device includes a third level, the third level including second transistors, and where the second device includes a fourth level, the fourth level including second interconnections, where the first device is substantially larger in area than the second device; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors.