Invention Grant
- Patent Title: Integrated circuit substrate and method of making
-
Application No.: US15721321Application Date: 2017-09-29
-
Publication No.: US10658281B2Publication Date: 2020-05-19
- Inventor: Rahul N. Manepalli , Kousik Ganesan , Marcel Arlan Wall , Srinivas Pietambaram
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H05K7/10
- IPC: H05K7/10 ; H05K7/12 ; H01L23/498 ; H01L23/66 ; H01L21/48 ; H01L23/00 ; H05K1/18 ; H05K1/11 ; H05K1/03 ; H05K3/10 ; C25D3/38 ; C25D5/02 ; C25D7/12

Abstract:
According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.
Public/Granted literature
- US20190103348A1 INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF MAKING Public/Granted day:2019-04-04
Information query