Invention Grant
- Patent Title: Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process
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Application No.: US16178241Application Date: 2018-11-01
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Publication No.: US10658257B1Publication Date: 2020-05-19
- Inventor: Dao-Long Chen , Chih-Pin Hung , Ming-Hung Chen
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Main IPC: H01L23/29
- IPC: H01L23/29 ; H01L23/498 ; H01L23/31 ; H01L21/56 ; H01L21/48 ; H01L23/00
Abstract:
A semiconductor package structure includes a semiconductor die, at least one wiring structure, an encapsulant and a plurality of conductive elements. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The encapsulant surrounds the semiconductor die. The encapsulant is formed from an encapsulating material, and a Young's Modulus of the encapsulant is from 0.001 GPa to 1 GPa. The conductive elements are embedded in the encapsulant, and are electrically connected to the at least one wiring structure.
Information query
IPC分类:
