Invention Grant
- Patent Title: Wafer-level optoelectronic packaging
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Application No.: US15802009Application Date: 2017-11-02
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Publication No.: US10656338B2Publication Date: 2020-05-19
- Inventor: Yee Loy Lam
- Applicant: POET TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: POET Technologies, Inc.
- Current Assignee: POET Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agent Tue Nguyen
- Main IPC: G02B6/12
- IPC: G02B6/12 ; G02B6/30 ; G02B6/136 ; G02B6/132 ; G02B6/122 ; G02B6/42 ; G02B6/36

Abstract:
A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
Public/Granted literature
- US20190129099A1 WAFER-LEVEL OPTOELECTRONIC PACKAGING Public/Granted day:2019-05-02
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