Invention Grant
- Patent Title: Low thermal budget top source and drain region formation for vertical transistors
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Application No.: US15894208Application Date: 2018-02-12
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Publication No.: US10651089B2Publication Date: 2020-05-12
- Inventor: Alexander Reznicek , Shogo Mochizuki , Oleg Gluschenkov
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/8234 ; H01L21/265 ; H01L27/088 ; H01L29/66
Abstract:
A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
Public/Granted literature
- US20190252260A1 LOW THERMAL BUDGET TOP SOURCE AND DRAIN REGION FORMATION FOR VERTICAL TRANSISTORS Public/Granted day:2019-08-15
Information query
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