Invention Grant
- Patent Title: Cut metal gate process for reducing transistor spacing
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Application No.: US16421532Application Date: 2019-05-24
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Publication No.: US10651030B2Publication Date: 2020-05-12
- Inventor: Ming-Chang Wen , Chang-Yun Chang , Hsien-Chin Lin , Hung-Kai Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/3215 ; H01L21/3105 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/8258 ; H01L21/8238 ; H01L21/762 ; H01L27/11 ; H01L27/02

Abstract:
A semiconductor structure includes a substrate; first and second fins extending from the substrate and oriented lengthwise generally along a first direction; an isolation feature over the substrate and separating bottom portions of the first and the second fins; first and second epitaxial semiconductor features over the first and the second fins, respectively; and a first dielectric feature sandwiched between the first and the second epitaxial semiconductor features. A maximum width of the first dielectric feature is smaller than a width of the isolation feature between the first and the second fins along a second direction perpendicular to the first direction.
Public/Granted literature
- US20190318922A1 Cut Metal Gate Process for Reducing Transistor Spacing Public/Granted day:2019-10-17
Information query
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