Invention Grant
- Patent Title: Reduction of stress in via structure
-
Application No.: US15850446Application Date: 2017-12-21
-
Publication No.: US10593616B2Publication Date: 2020-03-17
- Inventor: Toyohiro Aoki , Takashi Hisada , Akihiro Horibe , Sayuri Hada , Eiji I. Nakamura , Kuniaki Sueoka
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/498 ; H01L21/768

Abstract:
A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.
Public/Granted literature
- US20180294214A1 REDUCTION OF STRESS IN VIA STRUCTURE Public/Granted day:2018-10-11
Information query
IPC分类: