Invention Grant
- Patent Title: Memory circuit with leakage compensation
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Application No.: US16112402Application Date: 2018-08-24
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Publication No.: US10593413B2Publication Date: 2020-03-17
- Inventor: Stephen Keith Heinrich-Barna , Raviprakash Suryanarayana Rao
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Ebby Abraham; Charles A. Brill; Frank D. Cimino
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C5/00 ; G11C17/08 ; G11C7/18 ; G11C16/04 ; G11C16/26 ; G11C16/30

Abstract:
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
Public/Granted literature
- US20180366205A1 Memory Circuit with Leakage Compensation Public/Granted day:2018-12-20
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