Invention Grant
- Patent Title: Semiconductor memory device with correcting resistances in series with memory array signal lines
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Application No.: US15914687Application Date: 2018-03-07
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Publication No.: US10593375B2Publication Date: 2020-03-17
- Inventor: Kazuyo Ishii
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2017-177464 20170915
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C11/16 ; G11C13/00 ; G11C7/18 ; G11C8/10
Abstract:
According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.
Public/Granted literature
- US20190088289A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2019-03-21
Information query
