Invention Grant
- Patent Title: Drain extended NMOS transistor
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Application No.: US15830856Application Date: 2017-12-04
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Publication No.: US10580890B2Publication Date: 2020-03-03
- Inventor: Xiaoju Wu , Robert James Todd , Henry Litzmann Edwards
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L29/06 ; H01L29/40 ; H01L21/74 ; H01L21/762 ; H01L21/265 ; H01L21/324 ; H01L21/225 ; H01L21/285

Abstract:
A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.
Public/Granted literature
- US20190172946A1 DRAIN EXTENDED NMOS TRANSISTOR Public/Granted day:2019-06-06
Information query
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