- Patent Title: Memory interface and memory system including plurality of delay adjustment circuits shared by memory read and write circuits for adjusting the timing of read and write data signals
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Application No.: US16114177Application Date: 2018-08-27
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Publication No.: US10580467B2Publication Date: 2020-03-03
- Inventor: Hiroaki Iijima
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2018-050133 20180316
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/10 ; G06F13/16
Abstract:
A memory interface includes a first output circuit to be connected to the memory device for communication therewith, a first input circuit to be connected to the memory device for communication therewith, a first write circuit configured to process write data, a read circuit configured to process read data and a read strobe, a first delay adjustment circuit, a first switching circuit which is connected in a signal path between the first write circuit and the first delay adjustment circuit, and in a signal path between the first input circuit and the first delay adjustment circuit, and a second switching circuit which is connected in a signal path between the first delay adjustment circuit and the first output circuit, and in a signal path between the first delay adjustment circuit and the read circuit.
Public/Granted literature
- US20190287585A1 MEMORY INTERFACE AND MEMORY SYSTEM Public/Granted day:2019-09-19
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