Invention Grant
- Patent Title: Device, system and method for identifying a source of latency in pipeline circuitry
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Application No.: US15859016Application Date: 2017-12-29
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Publication No.: US10579492B2Publication Date: 2020-03-03
- Inventor: Jonathan Combs , Jason Brandt
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F11/34 ; G06F11/30 ; G06F9/54

Abstract:
Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.
Public/Granted literature
- US20190205236A1 DEVICE, SYSTEM AND METHOD FOR IDENTIFYING A SOURCE OF LATENCY IN PIPELINE CIRCUITRY Public/Granted day:2019-07-04
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