Invention Grant
- Patent Title: Multiplier circuit for accelerated square operations
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Application No.: US15627526Application Date: 2017-06-20
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Publication No.: US10579335B2Publication Date: 2020-03-03
- Inventor: Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh , Raghavan Kumar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F7/52
- IPC: G06F7/52 ; G06F7/523 ; G06F21/72 ; G06F21/60

Abstract:
In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.
Public/Granted literature
- US20180364982A1 MULTIPLIER CIRCUIT FOR ACCELERATED SQUARE OPERATIONS Public/Granted day:2018-12-20
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