Invention Grant
- Patent Title: Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures
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Application No.: US15896696Application Date: 2018-02-14
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Publication No.: US10566441B2Publication Date: 2020-02-18
- Inventor: Hao Nong , Liang Li , Chiew Wah Yap , Ting Huo , Yung Fu Chong , Yun Ling Tan
- Applicant: Globalfoundries Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Thompson Hine LLP
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/308 ; H01L21/311 ; H01L21/673 ; H01L21/768 ; H01L21/8234 ; H01L21/8238 ; H01L27/088 ; H01L29/66

Abstract:
Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.
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