Invention Grant
- Patent Title: NAND memory cell string having a stacked select gate structure and process for for forming same
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Application No.: US16452106Application Date: 2019-06-25
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Publication No.: US10566341B2Publication Date: 2020-02-18
- Inventor: Ming Sang Kwan , Shenqing Fang , Youseok Suh , Michael A. Van Buskirk
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/14 ; H01L27/1157 ; G11C16/16 ; H01L27/11582 ; H01L23/528 ; H01L29/16 ; H01L29/04 ; H01L29/51

Abstract:
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.
Public/Granted literature
- US20190326303A1 NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME Public/Granted day:2019-10-24
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