- Patent Title: Stacked complementary junction FETs for analog electronic circuits
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Application No.: US16399370Application Date: 2019-04-30
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Publication No.: US10553586B2Publication Date: 2020-02-04
- Inventor: Karthik Balakrishnan , Bahman Hekmatshoartabari , Alexander Reznicek , Jeng-Bang Yau
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent L. Jeffrey Kelly
- Main IPC: H01L27/098
- IPC: H01L27/098 ; H01L21/8232 ; H01L29/66 ; H01L29/808 ; H01L29/423 ; H01L29/10 ; H01L29/08 ; H01L21/822 ; H01L29/06 ; H01L27/06

Abstract:
A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
Public/Granted literature
- US20190259755A1 STACKED COMPLEMENTARY JUNCTION FETS FOR ANALOG ELECTRONIC CIRCUITS Public/Granted day:2019-08-22
Information query
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