Invention Grant
- Patent Title: Patterned gate dielectrics for III-V-based CMOS circuits
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Application No.: US16012056Application Date: 2018-06-19
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Publication No.: US10553584B2Publication Date: 2020-02-04
- Inventor: Takashi Ando , Martin M. Frank , Renee T. Mo , Vijay Narayanan , John Rozen
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L21/8258

Abstract:
Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
Public/Granted literature
- US20180308845A1 PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS Public/Granted day:2018-10-25
Information query
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