- Patent Title: Stacked semiconductor die assemblies with die substrate extensions
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Application No.: US16154659Application Date: 2018-10-08
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Publication No.: US10553566B2Publication Date: 2020-02-04
- Inventor: Fumitomo Watanabe , Keiyo Kusanagi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/065 ; H01L23/31 ; H01L23/29 ; H01L25/00 ; H01L21/56 ; H01L21/52

Abstract:
Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.
Public/Granted literature
- US20190043840A1 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUBSTRATE EXTENSIONS Public/Granted day:2019-02-07
Information query
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