Invention Grant
- Patent Title: Chip packaging method
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Application No.: US15751790Application Date: 2016-05-20
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Publication No.: US10553458B2Publication Date: 2020-02-04
- Inventor: Yuedong Qiu , Chengchung Lin
- Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Applicant Address: CN JiangYin
- Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee Address: CN JiangYin
- Agency: Alston & Bird LLP
- Priority: CN201510575637 20150910
- International Application: PCT/CN2016/082779 WO 20160520
- International Announcement: WO2017/041519 WO 20170316
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/56 ; H01L23/00

Abstract:
The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes.
Public/Granted literature
- US20190035642A1 CHIP PACKAGING METHOD Public/Granted day:2019-01-31
Information query
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