Invention Grant
- Patent Title: Systems and methods for semiconductor packages using photoimageable layers
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Application No.: US16317789Application Date: 2016-07-14
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Publication No.: US10553453B2Publication Date: 2020-02-04
- Inventor: Sri Chaitra Chavali , Siddharth K. Alur , Amanda E. Schuckman , Amruthavalli Palla Alur , Islam A. Salama , Yikang Deng , Kristof Darmawikarta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Eversheds Sutherland (US) LLP
- International Application: PCT/US2016/042285 WO 20160714
- International Announcement: WO2018/013121 WO 20180118
- Main IPC: H05K1/03
- IPC: H05K1/03 ; H05K3/00 ; H01L21/48 ; H01L23/498 ; H01L23/00 ; H01L23/522 ; H01L23/532

Abstract:
Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.
Public/Granted literature
- US20190311916A1 SYSTEMS AND METHODS FOR SEMICONDUCTOR PACKAGES USING PHOTOIMAGEABLE LAYERS Public/Granted day:2019-10-10
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