A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.